BPDL – Machine Description Language For Clustered VLIW Processors

Recent families of Digital Signal Processors show a VLIW-like architecture. These processors comprise of multiple execution units agglomerated into several data paths. With heavily pipelined, atomic RISC like operations, these are able to execute several instructions in a single cycle. The scheduling is done statically, and this saves hardware at the expense of more sophisticated compiler. This paper presents BPDL, a machine description language that delineates DSP processors that exhibit VLIW paradigm. BPDL represents the VLIW processor and its instruction set at a higher level of abstraction. The functional unit model that depicts the computational elements like Arithmetic Logic Unit (ALU), Multiply and Accumulate Unit (MAC), Address Generation Unit (AGU) etc characterizes general-purpose architecture. Data model is the representation of data holders like registers, instruction memory and data memory. The language has been employed to successfully model two of the most widely used VLIW DSPs i.e. TI’s TMS320c6x and StarCore’s SC140. Finally the BPDL processor model is given to the BURAQ tool suite, which allows cycle and bit accurate simulation and hardware generation of the architecture.